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[Other resource] asyn_FIFOrealizedbyVHDL

Description: 一个比较经典的用VHDL实现的FIFO论文
Platform: | Size: 53245 | Author: Roger | Hits:

[Other resource] uart_regs

Description: 可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。
Platform: | Size: 388297 | Author: liujingxing | Hits:

[USB develop] usb

Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码
Platform: | Size: 1012462 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] 9.16fifoasi

Description: 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Platform: | Size: 2761728 | Author: yjb_21cn | Hits:

[VHDL-FPGA-Verilog] my_fifo_vhdl

Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: | Size: 19456 | Author: 朱效志 | Hits:

[VHDL-FPGA-Verilog] fifo8_8

Description:
Platform: | Size: 1024 | Author: 李松 | Hits:

[VHDL-FPGA-Verilog] sopc_avalon_audio_dac_fifo

Description: fpga嵌入式系统组件，可以很方便的扩展，是个实例的例子，可以实现歌曲播放-FPGA embedded system components, it is easy to expand, is an example of the example, you can realize music player
Platform: | Size: 14336 | Author: dahai | Hits:

[VHDL-FPGA-Verilog] zzmodelsim

Description: verilog仿真工具modelsim的使用教程,幻灯片形式的,图文并茂,简单易学.经典的老教材-ModelSim Verilog simulation tool use tutorials, slide the form of illustrations, easy to learn. classic old material
Platform: | Size: 505856 | Author: oasis | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
Platform: | Size: 717824 | Author: 吴厚航 | Hits:

[VHDL-FPGA-Verilog] VGA-VerilogHDL

Description: 用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
Platform: | Size: 141312 | Author: liping | Hits:

[Graph Recognize] lcd-code

Description: 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
Platform: | Size: 1831936 | Author: 李佳 | Hits:

[VHDL-FPGA-Verilog] mini_fifo

Description: 另外一个用VHDL源码编写的FIFO模块程序,可以比较一下和FIFO有什么区别.-Another, prepared by using VHDL source FIFO module procedures, you can compare and What is the difference between FIFO.
Platform: | Size: 2048 | Author: falcon_cq | Hits:

[Software Engineering] 00837024

Description: 一个基于VHDL同步FIFO的设计思路的文章，以及一个编译完整的程序。-VHDL-based synchronous FIFO design ideas article, as well as a compiler procedures.
Platform: | Size: 224256 | Author: 飞仔 | Hits:

[VHDL-FPGA-Verilog] FIFO_EMIF

Description: 实现FPGA通过EMIF总线给DSP定期发送数据的功能-FPGA implementation through the EMIF bus regularly send data to the DSP function
Platform: | Size: 1480704 | Author: 徐成发 | Hits:

[VHDL-FPGA-Verilog] SYNC_FIFO

Description: its simple fifo.which is used to first in first out for vhdl source code
Platform: | Size: 1024 | Author: Viral | Hits:

[VHDL-FPGA-Verilog] FPGA_Design_Guide_Chapter1_Westor

Description:
Platform: | Size: 2136064 | Author: 陈枫 | Hits:

[VHDL-FPGA-Verilog] fifo_memory

Description: 用vhdl设计的一个FIFO存储器-Vhdl design with a FIFO memory
Platform: | Size: 1024 | Author: jiangp | Hits:

[VHDL-FPGA-Verilog] SDCard_Controller

Description: SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 -SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
Platform: | Size: 24576 | Author: xiafei | Hits:

[VHDL-FPGA-Verilog] fifo1

Description: 用VHDl写的FIFO 如果刚学VHDL 看看此程序很有用的-By the FIFO write VHDl learn if VHDL just take a look at this program very useful
Platform: | Size: 111616 | Author: 小胖 | Hits:
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